The methods described in the embodiments may be used for the formation, isolation, and exposure of semiconductor elements on microchip wafers. In particular, the methods may be used for the isolation and exposure of magnetic tunnel junction (MTJ) pillar arrays.
An MTJ is a semiconductor device that may be comprised of two ferromagnets separated by an insulator. In the context of a magnetoresistive random access memory (MRAM) device, an MTJ may comprise a free magnetic layer and a reference magnetic layer, each of which are separated by the insulator. Additional layers are used to create a memory cell such an MRAM device. An MTJ for an MRAM device may also include a hard-mask above the magnetic layers.
MRAM is able to store information because the resistance of the MTJ pillar changes based the direction of the magnetization of the free layer. When the device writes information, the direction of magnetization can be switched to change the resistance of the MTJ pillar. The resulting resistance of the MTJ pillar is interpreted as a digital “1” or “0”.
An example of a process for isolating, and then subsequently exposing MTJ pillars includes depositing a thick insulating layer to create bumps on the pillars and in valleys in the adjacent areas and then applying chemical mechanical polishing (“CMP”) and/or reactive-ion-etching (“RIE”) to remove the insulating layer until the top of the pillars are exposed.
However, this process has several drawbacks. As the CMP process progresses through the insulating layer, which can be very thick (hundreds of nanometers), determining when to stop the CMP process is very difficult. If the CMP process progresses too far, it can damage the pillars. In addition, the lack of CMP uniformity across the wafers can be significant, which negatively impacts the pillar height and size control.
FIG. 1A shows an example of a wafer array 100 containing MTJ pillars at locations 102, 104, and 106. If CMP is applied across the wafer, there will be significant deviation across the wafer in the height of the pillars. FIG. 1B, shows an example of a test wafer with the cross-section heights of MTJ pillars located at 102, 104 and 106. Specifically, in one test wafer, the height of the center pillar at 102 was 51 nanometers, the middle pillar at 104 was 39 nanometers, while the edge pillar at 106 was only 17 nanometers. The non-uniform polishing creates resistance uniformity issues between pillars and can cause damage to the pillars if the CMP removal is extreme. Such pillar damage includes micro-delamination, microcracks, and the creation of shunts.
These drawbacks cause wide-ranging problems with the MRAM incorporating the MTJ pillars. Damage and non-uniformity result in problematic tunnel magnetorestistance (“TMR”) values, poor property control, and shunts. The inability to precisely stop the CMP process at the appropriate time prevents the use of the short pillars required for higher density arrays for MRAM. Alternative etching processes do not provide better control or across wafer uniformity.
Thus, there is a need in the art for a manufacturing process that is capable of insulating and subsequently exposing semiconductor elements that is consistent across a wafer, provides consistently high TMR values for large readout signals, allows for higher area density, has little risk of damaging or creating problems in the pillars, and can be performed easily at low cost.